Texas Instruments TMS320C3x 사용자 설명서

Reset Operation

7-21

Program Flow Control

7.5

Reset Operation

The ’C3x supports a nonmaskable external reset signal (RESET), which is
used to perform system reset. This section discusses the reset operation.

At start-up, the state of the ’C3x processor is undefined. You can use the RESET
signal to place the processor in a known state. This signal must be asserted low
for ten or more H1 clock cycles to guarantee a system reset. H1 is an output
clock signal generated by the ’C3x. (Check the datasheet for your device for the
specific signal descriptions and electrical characteristics.)

Reset affects the other pins on the device in either a synchronous or asynchro-
nous manner. The synchronous reset is gated by the ’C3x’s internal clocks. The
asynchronous reset directly affects the pins and is faster than the synchronous
reset. Table 7–3 shows the state of the ’C3x’s pins after RESET = 0. Each pin is
described according to whether the pin is reset synchronously or asynchronously.

Table 7–3. TMS320C3x Pin Operation at Reset

Device

Signal

Operation at Reset

‘C30

‘C31

‘C32

Primary Bus Interface Signals

D31 – D0

Synchronous reset; placed in high-impedance state

A23 – A0

Synchronous reset; placed in high-impedance state

R/W