Texas Instruments TMS320C3x 사용자 설명서

Interrupts

7-37

Program Flow Control

Figure 7–7. Interrupt Logic Functional Diagram

INTn

To
control
section

Internal interrupt

set signal

Interrupt

flag (n)

Internal

interrupt

processor

Internal interrupt

clear/acknowledge

signal

EINTn(DMA)

EINTn(CPU)

H1

H3

H1

D

CLK

D

CLK

D

CLK

Set

RESET

GIE(CPU)

Q

Q

Q

Q

These interrupts are prioritized by the selection of one over the other if both
come on the same clock cycle (INT0 the highest, INT1 next, etc.). When an
interrupt is taken, the status register ST(GIE) bit is reset to 0, disabling any other
incoming interrupt. This prevents any other interrupt (INT0 – INT3) from assuming
program control until the ST(GIE) bit is set back to 1. On a return from an interrupt
routine, the RETI and RETI

cond instructions set the ST(GIE) bit to 1.

On the ‘C30 and ‘C31, external interrupts are level triggered. On the ‘C32,
external interrupts are edge or level triggered, depending on the INT config
bit field of the status register.

For an edge-triggered interrupt to be detected by the ’C32 the external pin
must transition from 1 to 0. And then, it needs to be held low for at least one
H1/H3 cycle (but it could be held low longer).

For a level-triggered interrupt to be detected by the ’C3x, the external pin must
be held low for between one and two cycles (1

v

low-pulse width

v

2). If the

interrupt is held low for more than two cycles, more than one interrupt might
be recognized. There is no need to provide an edge in this case.