Texas Instruments TMS320C3x 사용자 설명서

Clocking Memory Accesses

8-26

If both source operands are to be fetched from memory, then memory reads
can occur in several ways:

If both operands are located in internal memory, the

src1 read is performed

during H3 and the

src2 read during H1, completing two memory reads in

a single cycle.

src1 is in internal memory and src2 is in external memory, the src2 access

begins at the start of H3 and latches at the end of H1. At the same time, the
src1 access to internal memory is performed during H3. Again, two memory
reads are completed in a single cycle.

src1 is in external memory and src2 is in internal memory, two cycles are

necessary to complete the two reads. In the first cycle, both operands are
addressed. Since

src1 takes an entire cycle to be read and latched from

external memory, the internal operation on

src2 cannot be completed until

the second cycle. Ordering the operands so that

src1 is located internally

is necessary to achieve single-cycle execution.

src1 and src2 are both from external memory, two cycles are required to

complete the two reads. In the first cycle, the

src1 access is performed and

loaded on the next H3; in the second cycle, the

src2 access is performed

and loaded on that cycle’s H1.

src2 is in external memory and src1 is in on-chip or external memory and is

immediately preceded by a single store instruction to external memory, a
dummy

src2 read can occur between the execution of the store instruction and

the

src2 read, regardless of which memory space is accessed (STRB, MSTRB,

or IOSTRB). The dummy read can cause an externally interfaced FIFO address
pointer to be incremented prematurely, thereby causing the loss of FIFO data.
Example 8–17 illustrates how the dummy read can occur. Example 8–18 offers
an alternative code segment that suppresses the dummy read. In the alternative
code segment, the dummy read is eliminated by swapping the order of the
source operands.