Texas Instruments TMS320C3x 사용자 설명서
External Memory Interface Timing
9-21
TMS320C30 and TMS320C31 External-Memory Interface
9.6.2
Expansion-Bus I/O Cycles
In contrast to primary bus and MSTRB cycles, IOSTRB reads and writes are
both two cycles in duration (with no wait states) and exhibit the same timing.
During these cycles, address always changes on the falling edge of H1, and
IOSTRB is low from the rising edge of the first H1 cycle to the rising edge of
the second H1 cycle. The IOSTRB signal always goes inactive (high) between
cycles, and XR/W is high for reads and low for writes.
both two cycles in duration (with no wait states) and exhibit the same timing.
During these cycles, address always changes on the falling edge of H1, and
IOSTRB is low from the rising edge of the first H1 cycle to the rising edge of
the second H1 cycle. The IOSTRB signal always goes inactive (high) between
cycles, and XR/W is high for reads and low for writes.
Figure 9–10 illustrates read and write cycles when IOSTRB is active and there
are no wait states. For IOSTRB accesses, reads and writes require a minimum
of two cycles. Some off-chip peripherals might change their status bits when
read or written to. Therefore, it is important to maintain valid addresses when
communicating with these peripherals. For reads and writes when IOSTRB is
active, IOSTRB is completely framed by the address.
are no wait states. For IOSTRB accesses, reads and writes require a minimum
of two cycles. Some off-chip peripherals might change their status bits when
read or written to. Therefore, it is important to maintain valid addresses when
communicating with these peripherals. For reads and writes when IOSTRB is
active, IOSTRB is completely framed by the address.
Figure 9–10. Read and Write for IOSTRB = 0
H3
H1
XA
XD
XR/W
IOSTRB
XRDY
Read
Write data