Texas Instruments TMS320C3x 사용자 설명서
Programmable Bank Switching
10-18
The ’C3x has an internal register that contains the MSBs (as defined by the
BNKCMP field) of the last address used for a read or write over the primary inter-
face. At reset, the register bits are set to 0. If the MSBs of the address being used
for the current primary interface read do not match those contained in this inter-
nal register, a read cycle is not asserted for one H1/H3 clock cycle. During this
extra clock cycle, the address bus switches over to the new address, but STRB
is inactive (high). The contents of the internal register are replaced with the
MSBs being used for the current read of the current address. If the MSBs of the
address being used for the current read match the bits in the register, a normal
read cycle takes place.
BNKCMP field) of the last address used for a read or write over the primary inter-
face. At reset, the register bits are set to 0. If the MSBs of the address being used
for the current primary interface read do not match those contained in this inter-
nal register, a read cycle is not asserted for one H1/H3 clock cycle. During this
extra clock cycle, the address bus switches over to the new address, but STRB
is inactive (high). The contents of the internal register are replaced with the
MSBs being used for the current read of the current address. If the MSBs of the
address being used for the current read match the bits in the register, a normal
read cycle takes place.
If repeated reads are performed from the same memory bank, no extra cycles
are inserted. When a read is performed from a different memory bank, memory
conflicts are avoided by the insertion of an extra cycle. This feature can be
disabled by setting BNKCMP to 0. The insertion of the extra cycle occurs only
when a read is performed. The changing of the MSBs in the internal register
occurs for all reads and writes over the primary interface.
are inserted. When a read is performed from a different memory bank, memory
conflicts are avoided by the insertion of an extra cycle. This feature can be
disabled by setting BNKCMP to 0. The insertion of the extra cycle occurs only
when a read is performed. The changing of the MSBs in the internal register
occurs for all reads and writes over the primary interface.
Figure 9–5 shows the addition of an inactive cycle when switches between
banks of memory occur.
banks of memory occur.
Figure 10–9. Bank-Switching Example
Read
H3
H1
STRB
R/W
A
D
RDY
Read
Extra
cycle
cycle
Read