Texas Instruments TMS320C3x 사용자 설명서
External Ready Timing Improvement
10-38
10.9 External Ready Timing Improvement
The ready (RDY) timing should relate to the H1 low signal as shown in
Figure 10–22. This is equivalent to the ’C4x ready timing, which increases the
time between valid address and the sampling of RDY. This facilitates the memory
hardware interface by allowing a longer address decode-circuit response time to
generate a ready signal.
Figure 10–22. This is equivalent to the ’C4x ready timing, which increases the
time between valid address and the sampling of RDY. This facilitates the memory
hardware interface by allowing a longer address decode-circuit response time to
generate a ready signal.
Figure 10–22. RDY Timing for Memory Read
RDY
D
A
R/W
STRBx
H1
H3
Data
Address
tsu(RDY)
Do not change the RDY signal during its setup time [
t
su(RDY)].