Texas Instruments TMS320C3x 사용자 설명서
Bus Timing
10-42
Figure 10–26. One Wait-State Write Sequence for STRBx Active
RDY
D
A
R/W
STRBx
H1
H3
Extra cycle
Write
10.10.2
IOSTRB Bus Cycles
In contrast to STRB0 and STRB1 bus cycles, IOSTRB full speed (zero wait-
state) reads and writes consume two H1 cycles. During these cycles, the
IOSTRB signal is low from the rising edge of the first H1 cycle to the rising edge
of the second H1 cycle. Also, the address changes on the falling edge of the
first H1 cycle and R / W changes state on the falling edge of H1. This provides
a valid address to peripherals that may change their status bits when read or
written while IOSTRB is active. Moreover, the IOSTRB signal is high between
IOSTRB read and write cycles.
state) reads and writes consume two H1 cycles. During these cycles, the
IOSTRB signal is low from the rising edge of the first H1 cycle to the rising edge
of the second H1 cycle. Also, the address changes on the falling edge of the
first H1 cycle and R / W changes state on the falling edge of H1. This provides
a valid address to peripherals that may change their status bits when read or
written while IOSTRB is active. Moreover, the IOSTRB signal is high between
IOSTRB read and write cycles.