Texas Instruments TMS320C3x 사용자 설명서
TMS320C32 Boot Loader
11-23
Using the TMS320C31 and TMS320C32 Boot Loaders
11.2.5 Boot-Loader Hardware Interface
The hardware interface for the memory boot load uses the STRBX_B3 through
STRBX_B0 pins as strobe byte-enable pins (see Figure 11–8). The hardware
interface is independent of the boot source memory width. This interface
is identical to the 32-bit-wide memory interface described in Case 2, in Section
10.6 on page 10-20. For 16-bit memory widths, remove the two left-most
memory devices of Figure 11–8. For 8-bit memory widths, remove all but the
right-most of the memory devices of Figure 11–8.
STRBX_B0 pins as strobe byte-enable pins (see Figure 11–8). The hardware
interface is independent of the boot source memory width. This interface
is identical to the 32-bit-wide memory interface described in Case 2, in Section
10.6 on page 10-20. For 16-bit memory widths, remove the two left-most
memory devices of Figure 11–8. For 8-bit memory widths, remove all but the
right-most of the memory devices of Figure 11–8.
Figure 11–8. External Memory Interface for Source Data Stream Memory Boot Load
’C32
STRBX_B3
STRBX_B2
STRBX_B1
STRBX_B0
STRBX_B2
STRBX_B1
STRBX_B0
D(31–24)
D(23–16)
D(23–16)
D(15–8)
D(7–0)
I/O(7-
0)
A
23
A
22
A
21
A
20
A
2
A
1
A
0
. . .
. . .
A
23
A
22
A
21
A
20
A
2
A
1
A
0
. . .
CS
I/O(7-
0)
. . .
A
23
A
22
A
21
A
20
A
2
A
1
A
0
. . .
CS
I/O(7-
0)
. . .
A
23
A
22
A
21
A
20
A
2
A
1
A
0
. . .
CS
I/O(7-
0)
. . .
A
23
A
22
A
21
A
20
A
2
A
1
A
0
. . .
CS
16–bit wide EPROM
32–bit wide EPROM
8–bit wide EPROM
11.2.6 TMS320C32 Boot-Loader Precautions
The interrupt flags are not reset by the boot-loader function. If pending interrupts
are to be avoided when interrupts are enabled, clear the IF register before enabling
interrupts.
are to be avoided when interrupts are enabled, clear the IF register before enabling
interrupts.
The MCBL/MP pin should remain high during the entire boot-loading execution,
but it can be changed subsequently at any time. The ’C32 does not need to be
reset after the MCBL/MP pin is changed. During the change, the ’C32 should
not access addresses Oh–FFh. The memory space Oh–FFFh is mapped to
external memory three clock cycles after changing the MCBL/MP pin.
but it can be changed subsequently at any time. The ’C32 does not need to be
reset after the MCBL/MP pin is changed. During the change, the ’C32 should
not access addresses Oh–FFh. The memory space Oh–FFFh is mapped to
external memory three clock cycles after changing the MCBL/MP pin.