Texas Instruments TMS320C3x 사용자 설명서

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Serial Ports
 
12-38
sync inputs are ignored. Additionally, you should set R/XFSM prior to or
during the first word transferred; you must set R/XFSM no later than the
transfer of the 
N–1 bit of the first word, except for transmit operations. For
transmit operations in the fixed data-rate mode, XFSM must be set no later
than the 
N–2 bit. You must clear R/XFSM no later than the N–1 bit to be
recognized in the current cycle.
Figure 12–28. Fixed Continuous Mode Without Frame Sync
DR/DX
FSX (internal)
FSR/FSX (external)
CLKX/R
A1
AN
B1
BN
C1
DXR loaded
XINT
DXR loaded
Set
R/XFSM
XINT
RINT
Load DXR
read DRR
XINT
RINT
Load DXR
read DRR
R/XVAREN = 0
R/XFSM = 1
The timing of RINT and XINT and data transfers to and from DXR and
DRR, respectively, are the same as in fixed data-rate standard mode with
back-to-back frame syncs. This mode of operation also exhibits the same
delay of 2.5 CLKX cycles after DXR is loaded before an internal FSX is
generated. As in the case of continuous operation in fixed data-rate mode
with frame sync, you must reload DXR no later than transmission of the
N–3 bit.
-
Enabling or Disabling Frame Syncs in Fixed Mode
When you use continuous operation in fixed data-rate mode, you can set
and clear R/XFSM as desired, even during active transfers, to enable or
disable the use of frame sync pulses as dictated by system requirements.
Under most conditions, changing the state of R/XFSM occurs during the
transfer in which the R/XFSM change was made, provided the change
was made early enough in the transfer. For transmit operations with inter-
nal FSX in fixed data-rate mode, however, a 1-word delay occurs before
frame sync pulse generation resumes when clearing XFSM to 0 (see
Figure 12–29). In this case, one additional word is transferred before the
next FSX pulse is generated. The clearing of XFSM is recognized during
the transmission of the word currently being transmitted as long as XFSM
is cleared no later than the 
N–1 bit. The setting of XFSM is recognized as
long as XFSM is set no later than the
 N–2 bit.