Texas Instruments TMS320C3x 사용자 설명서
DMA Controller
12-48
12.3 DMA Controller
The DMA controller is a programmable peripheral that transfers blocks of data
to any location in the memory map without interfering with CPU operation. The
’C3x can interface to slow, external memories and peripherals without reducing
throughput to the CPU. The ’C3x DMA controller features are:
to any location in the memory map without interfering with CPU operation. The
’C3x can interface to slow, external memories and peripherals without reducing
throughput to the CPU. The ’C3x DMA controller features are:
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Transfers to and from anywhere in the processor’s memory map. For
example, transfers can be made to and from on-chip memory, off-chip
memory, and on-chip serial ports.
example, transfers can be made to and from on-chip memory, off-chip
memory, and on-chip serial ports.
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One DMA channel for memory-to-memory transfers in ‘C30 and ‘C31. Two
DMA channels for memory-to-memory transfers in ‘C32.
DMA channels for memory-to-memory transfers in ‘C32.
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Concurrent CPU and DMA controller operation with DMA transfers at the
same rate as the CPU (supported by separate internal DMA address and
data buses).
same rate as the CPU (supported by separate internal DMA address and
data buses).
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Source and destination-address registers with auto increment/decrement.
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Synchronization of data transfers via external and internal interrupts.
12.3.1 DMA Functional Description
The DMA controller supports one (‘C30 and ‘C31) or two (‘C32) DMA channels
that perform transfers to and from anywhere in the ‘C3x memory map.
that perform transfers to and from anywhere in the ‘C3x memory map.
Each DMA channel is controlled by four registers that are mapped in the ‘C3x
peripheral address space, as shown in Figure 12–35. The major DMA registers
are described in Section 12.3.3.
peripheral address space, as shown in Figure 12–35. The major DMA registers
are described in Section 12.3.3.
The DMA controller has dedicated on-chip address and data buses (see
Figure 2–5 through Figure 2–7 on pages 2-14 through 2-16 for a block dia-
gram of the peripherals of the ‘C3x). All accesses made by the DMA channels
are arbitrated in the DMA controller and take place over these dedicated
buses. The DMA channels transfer data in a sequential time-slice fashion,
rather than simultaneously, because they share common buses.
Figure 2–5 through Figure 2–7 on pages 2-14 through 2-16 for a block dia-
gram of the peripherals of the ‘C3x). All accesses made by the DMA channels
are arbitrated in the DMA controller and take place over these dedicated
buses. The DMA channels transfer data in a sequential time-slice fashion,
rather than simultaneously, because they share common buses.
The DMA channels can run constantly or can be triggered by external (INT3–0)
or internal (on-chip timers and serial ports) interrupts.
or internal (on-chip timers and serial ports) interrupts.