Texas Instruments TMS320C3x 사용자 설명서
DMA Controller
12-59
Peripherals
Figure 12–40. Transfer-Counter Operation
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Halt
?
TC=1
Is
DMA interrupt generated
?
TCINT=1
Is
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to 0
Compare
Decrementer
Transfer-counter register
Yes
Yes
No
No
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No
12.3.4 CPU/DMA Interrupt-Enable Register
The CPU/DMA interrupt-enable register (IE) is a 32-bit register located in the
CPU register file. The CPU interrupt-enable bits are in locations 10–1. The DMA
interrupt-enable bits are in locations 26–16. A 1 in a CPU/DMA interrupt-enable
register bit enables the corresponding interrupt. A 0 disables the corresponding
interrupt. At reset, 0 is written to this register.
CPU register file. The CPU interrupt-enable bits are in locations 10–1. The DMA
interrupt-enable bits are in locations 26–16. A 1 in a CPU/DMA interrupt-enable
register bit enables the corresponding interrupt. A 0 disables the corresponding
interrupt. At reset, 0 is written to this register.
Figure 12–41 shows the CPU/DMA interrupt-enable registers for the ‘C30 and
‘C31. Figure 12–42 shows the CPU/DMA interrupt-enable register for the ‘C32.
Table 12–7 describes the register bits, bit names, and bit functions.
‘C31. Figure 12–42 shows the CPU/DMA interrupt-enable register for the ‘C32.
Table 12–7 describes the register bits, bit names, and bit functions.