Texas Instruments TMS320C3x 사용자 설명서

DMA Controller

 

12-74

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The transfer counter has a zero value. However, the transfer counter is
decremented after the DMA read operation finishes (not after the write
operation). Nevertheless, a transfer counter with a 0 value can be used as
an indication of a transfer completion.

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The STAT bits in the DMA channel-control register are set to 00

2

. You can

poll the DMA channel-control register for this value. However, because the
DMA registers are memory-mapped into the peripheral bus address
space, this option can cause further CPU/DMA access conflicts.

Example 12–8, Example 12–9, and Example 12–10 illustrate initialization
procedures for the DMA.

When linking the examples, you should allocate section memory addresses
carefully to avoid CPU-DMA conflict. In the C3x, the CPU always prevails in
cases of conflict. In the event of a CPU program/DMA data conflict, cache
enabling helps if the 

.text section is in external memory. For example, when

linking the code in Example 12–8, Example 12–9, and Example 12–10, the
.text section can be allocated into RAM0, .data into RAM1, and .bss into
RAM1, where RAM0 corresponds to on-chip RAM block 0 and RAM1 corre-
sponds to on-chip RAM block 1.

In Example 12–8, the DMA initializes a 128-element array to 0. The DMA
sends an interrupt to the CPU after the transfer is completed. This program as-
sumes previous initialization of the CPU interrupt-vector table (specifically the
DMA-to-CPU interrupt). The program initializes the ST and IE registers for
interrupt processing.