Texas Instruments TMS320C3x 사용자 설명서

Instruction Set Summary

 

13-16

Table 13–8. Instruction Set Summary (Continued)

SUBI

Subtract integers

Dreg – 

src 

→

 Dreg

SUBI3

Subtract integers (3-operand)

src1 – src2 

→

 Dreg

SUBRB

Subtract reverse integer with borrow

src – Dreg – C 

→

 Dreg

SUBRF

Subtract reverse floating-point value

src – Rn 

→

R

n

SUBRI

Subtract reverse integer

src – Dreg 

→

 Dreg

SWI

Software interrupt

Perform emulator interrupt sequence

TRAP

cond

Trap conditionally

If 

cond = true or missing:

Next PC 

→

 * ++ SP

Trap vector N 

→

 PC

0 

→

 ST (GIE)

Else, continue

TSTB

Test bit fields

Dreg AND 

src

TSTB3

Test bit fields (3-operand)

src1 AND src2

XOR

Bitwise-exclusive OR

Dreg XOR 

src 

→

 Dreg

XOR3

Bitwise-exclusive OR (3-operand)

src1 XOR src2 

→

 Dreg

AR

n

auxiliary register 

n

 (AR7–AR0)

RE

repeat interrupt register

C

carry bit

RM

repeat mode bit

C

src

conditional-branch addressing modes

R

n

register address (R7–R0)

count

shift value (general addressing modes)

RS

repeat start register

cond

condition code

SP

stack pointer

Daddr

destination memory address

Sreg

register address (any register)

Dreg

register address (any register)

ST

status register

GIE

global interrupt enable register

src

general addressing modes

N

any trap vector 0–27

src

1

3-operand addressing modes

PC

program counter

src

2

3-operand addressing modes

RC

repeat counter register

TOS

top of stack