Texas Instruments TMS320C3x 사용자 설명서

Individual Instructions

13-33

Assembly Language Instructions

Table 13–13. Instruction Symbols

src
src1
src2
src3
src4

Source operand
Source operand 1
Source operand 2
Source operand 3
Source operand 4

dst
dst1
dst2
disp
cond
count

Destination operand
Destination operand 1
Destination operand 2
Displacement
Condition
Shift count

G
T
P
B

General addressing modes
3-operand addressing modes
Parallel addressing modes
Conditional-branch addressing modes

|

x|

x 

→

 

y

x(man)
x(exp)

Absolute value of x
Assign the value of x to destination y
Mantissa field (sign + fraction) of x
Exponent field of x

op1
|| 

op2

Operation 1 performed in parallel with operation 2

x AND y
x OR y
x XOR y

∼

x

Bitwise-logical AND of x and y
Bitwise-logical OR of x and y
Bitwise-logical XOR of x and y
Bitwise-logical complement of x

x << y
x >> y
*++SP
*SP– –

Shift x to the left y bits
Shift x to the right y bits
Increment SP and use incremented SP as address
Use SP as address and decrement SP

AR

n

IR

n

R

n

RC
RE
RS
ST

Auxiliary register 

n

Index register 

n

Register address 

n

Repeat count register
Repeat end address register
Repeat start address register
Status register

C
GIE
N
PC
RM
SP

Carry bit
Global interrupt enable bit
Trap vector
Program counter
Repeat mode flag
System stack pointer