Texas Instruments TMS320C3x 사용자 설명서

 Example Instruction

13-39

  Assembly Language Instructions

INST1



INST2

31

24 23

16

8 7

0

15

0 0 0

src

dst

G

31

24 23

16

8 7

0

15

1 1

dst

1

src

2

dst

2

src

3

0 0 0

or

INST

Encoding examples are shown using general addressing and parallel addressing.
The instruction pair for the parallel addressing example consists of INST1 and
INST2.

Instruction execution and its effect on the rest of the processor or memory con-
tents is described. Any constraints on the operands imposed by the processor
or the assembler are discussed. The description parallels and supplements
the information given by the operation block.

1

The digit specifies the number of cycles required to execute the instruction.

Latched floating-point underflow condition flag. 1 if a
floating-point underflow occurs; unchanged otherwise.

Latched overflow condition flag. 1 if an integer or floating-point
overflow occurs; unchanged otherwise.

Floating-point underflow condition flag. 1 if a floating-point underflow
occurs; 0 otherwise.

Negative condition flag. 1 if a negative result is generated; 0 other-
wise. In some instructions, this flag is the MSB of the output.

Zero condition flag. 1 if a 0 result is generated; 0 otherwise. For logical
and shift instructions, 1 if a 0 output is generated; 0 otherwise.

Overflow condition flag. 1 if an integer or floating-point overflow
occurs; 0 otherwise.

Carry flag. 1 if a carry or borrow occurs; 0 otherwise. For shift instruc-
tions, this flag is set to the value of the last bit shifted out; 0 for a shift
count of 0.

The seven condition flags stored in the status register (ST) are modified by the
majority of instructions only if the destination register is R7–R0. The flags  pro-
vide information about the properties of the result or the output of arithmetic
or logical operations.

OVM Overflow mode flag.  In general, integer operations are affected by the
OVM bit value (described in Table 3–2 on page 3-6).