Texas Instruments TMS320C3x 사용자 설명서

Add Integer, 3-Operand

13-58

 

<src2 >,<src1 >,<dst >

src1 + src2 

→

 dst

src1 3-operand addressing modes (T):

0 0

any CPU register

0 1

indirect (

disp = 0, 1, IR0, IR1)

1 0

any CPU register

1 1

indirect (

disp = 0, 1, IR0, IR1)

src2 3-operand addressing modes (T):

0 0

any CPU register

0 1

any CPU register

1 0

indirect (

disp = 0, 1, IR0, IR1)

1 1

indirect (

disp = 0, 1, IR0, IR1)

dst  any CPU register

31

24 23

16

8 7

0

15

0 0 1 0 0 0

0

T

src

2

dst

src

1

1

0

The sum of the 

src1 and src2 operands is loaded into the dst register. The src1,

src2, and dst operands are assumed to be signed integers.

1

These condition flags are modified only if the destination register is R7 – R0.

Unaffected

1 if an integer overflow occurs; unchanged otherwise

0

1 if a negative result is generated; 0 otherwise

1 if a 0 result is generated; 0 otherwise

1 if an integer overflow occurs; 0 otherwise

1 if a carry occurs; 0 otherwise

Operation is affected by OVM bit value.