Texas Instruments TMS320C3x 사용자 설명서

Internal Bus Operation

 

2-18

Much of the ’C3x’s high performance is due to internal busing and parallelism.
Separate buses allow for parallel program fetches, data accesses, and DMA
accesses:

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Program buses: PADDR and PDATA

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Data buses: DADDR1, DADDR2, and DDATA

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DMA buses: DMAADDR and DMADATA

These buses connect all of the physical spaces (on-chip memory, off-chip
memory, and on-chip peripherals) supported by the ’C3x. Figure 2–5,
Figure 2–6, and Figure 2–7 show these internal buses and their connections
to on-chip and off-chip memory blocks.

The program counter (PC) is connected to the 24-bit program address bus
(PADDR). The instruction register (IR) is connected to the 32-bit program data
bus (PDATA). These buses can fetch a single instruction word every machine
cycle.

The 24-bit data address buses (DADDR1 and DADDR2) and the 32-bit data
data bus (DDATA) support two data-memory accesses every machine cycle.
The DDATA bus carries data to the CPU over the CPU1 and CPU2 buses. The
CPU1 and CPU2 buses can carry two data-memory operands to the multiplier,
ALU, and register file every machine cycle. Also internal to the CPU are register
buses REG1 and REG2, which can carry two data values from the register file
to the multiplier and ALU every machine cycle. Figure 2–4 shows the buses
internal to the CPU section of the processor.

The DMA controller is supported with a 24-bit address bus (DMAADDR) and
a 32-bit data bus (DMADATA). These buses allow the DMA to perform memory
accesses in parallel with the memory accesses occurring from the data and
program buses.