Texas Instruments TMS320C3x 사용자 설명서

 Decrement and Branch Conditionally (Standard)

13-95

  Assembly Language Instructions

cond  ARn, src

AR

n – 1 

→

 AR

n

If 

cond is true and ARn 

≥

 0 :

If

 src is in register addressing mode (Rn, 0 

≤

n 

≤

 27),

src 

→

 PC.

If 

src is in PC-relative mode (label or address),

displacement + PC + 1 

→

 PC.

Else, continue

src conditional-branch addressing modes (B):

0

register

1

PC relative

AR

n register (0 

≤

 

n 

≤

 7)

31

24 23

16

8 7

0

15

0 1 1 0 1 1 B

0

cond

Register or displacement

AR

n

DB

cond signifies a standard branch that executes in four cycles because the

pipeline must be flushed if 

cond is true. The specified auxiliary register is de-

cremented and a branch is performed if the condition is true and the specified
auxiliary register is greater than or equal to 0. The condition flags are those set
by the last previous instruction that affects the status bits.

The auxiliary register is treated as a 24-bit signed integer. The 8 MSBs are un-
modified by the decrement operation. The comparison of the auxiliary register
uses only the 24 LSBs of the auxiliary register. Note that the branch condition
does not depend on the auxiliary register decrement.

If the

 src operand is expressed in register addressing mode, the contents of

the specified register are loaded into the PC. If the 

src operand is expressed

in PC-relative addressing mode, the assembler generates a displacement:
displacement = label – (PC of branch instruction + 1). This integer is stored as
a 16-bit signed integer in the 16 LSBs of the branch instruction word. This dis-
placement is added to the PC of the branch instruction plus 1 to generate the
new PC.

The ’C3x provides 20 condition codes that can be used with this instruction
(see Table 13–12 on page 13-30 for a list of condition mnemonics, condition
codes, and flags). Condition flags are set on a previous instruction only when
the destination register is one of the extended-precision registers (R0–R7) or
when one of the compare instructions (CMPF, CMPF3, CMPI, CMPI3, TSTB,
or TSTB3) is executed.