Texas Instruments TMS320C3x 사용자 설명서
Parallel LDI and LDI
LDI||LDI
13-129
Assembly Language Instructions
Syntax
LDI
src2, dst2
||
LDI
src1, dst1
Operation
src2
→
dst2
||
src1
→
dst1
Operands
src1
indirect (
disp = 0, 1, IR0, IR1)
dst1
register (R
n1, 0
≤
n1
≤
7)
src2
indirect (
disp = 0, 1, IR0, IR1)
dst2
register (R
n2, 0
≤
n2
≤
7)
This instruction’s operands have been augmented on the following devices:
-
’C31 silicon revision 6.0 or greater
-
’C32 silicon revision 2.0 or greater
src1
indirect (
disp = 0, 1, IR0, IR1)
dst1
register (R
n1, 0
≤
n1
≤
7)
src2
indirect (
disp = 0, 1, IR0, IR1) or any CPU register
dst2
register (R
n2, 0
≤
n2
≤
7)
Opcode
31
24 23
16
8 7
0
15
1 1 0 0 0 1
dst
2
src
2
src
1
1
dst
1
0 0 0
Description
Two integer loads are performed in parallel. The assembler issues a warning
if the LDIs load the same register. The result is that of LDI
if the LDIs load the same register. The result is that of LDI
src2, dst2.
Cycles
1
Status Bits
LUF
Unaffected
LV
Unaffected
UF
Unaffected
N
Unaffected
Z
Unaffected
V
Unaffected
C
Unaffected
OVM
Operation is not affected by OVM bit value.
Mode Bit