Texas Instruments TMS320C3x 사용자 설명서

Logical Shift

13-136

 

LSH  

count, dst

If 

count 

≥

 0:

dst << count 

→

 

dst

Else:

dst >> |count | 

→

 

dst

count general addressing modes (G):

0 0

any CPU register

0 1

direct

1 0

indirect (disp = 0–255, IR0, IR1)

1 1

immediate

dst  any CPU register

31

24 23

16

8 7

0

15

0 0 0

0 1

1

0

1

0

dst

count

G

The seven LSBs of the 

count operand are used to generate the 2s-comple-

ment shift count. If the 

count operand is greater than 0, the dst operand is left

shifted by the value of the 

count operand. Low-order bits shifted in are zero

filled, and high-order bits are shifted out through the carry (C) bit.

Logical left shift:

C 

←

 

dst 

←

 0

If the 

count operand is less than 0, the dst is right shifted by the absolute value

of the 

count operand. The high-order bits of the dst operand are zero filled as

they are shifted to the right. Low-order bits are shifted out through the C bit.

Logical right shift:

0 

→

 

dst 

→

 C

If the 

count operand is 0, no shift is performed, and the C bit is set to 0. The

count operand is assumed to be a signed integer, and the dst operand is as-
sumed to be an unsigned integer.