Texas Instruments TMS320C3x 사용자 설명서
MPYF3||ADDF3
Parallel MPYF3 and ADDF3
13-150
This instruction’s operands have been augmented in the following
devices:
devices:
-
’C31 silicon version 6.0 or greater
-
’C32 silicon version 2.0 or greater
srcA, srcB, srcC, srcD can be one of the following combinations:
Register
(0
v
R
n
v
7)
Indirect
(
disp = 0, 1, IR0, IR1)
Any CPU Register
2
2
–
2
1
1
2
–
2
dst1
register (
d1):
0 = R0
1 = R1
1 = R1
dst2
register (
d2):
0 = R2
1 = R3
1 = R3
src1
register (R
n, 0
≤
n
≤
7)
src2
register (R
n, 0
≤
n
≤
7)
src3
indirect (
disp = 0, 1, IR0, IR1) or any CPU register
src4
indirect (
disp = 0, 1, IR0, IR1) or any CPU register
P
parallel addressing modes (0
≤
P
≤
3)
Version 4.7 or earlier of TMS320 floating-point code-generation tools
P
srcA
srcB srcD
srcC
00
src4
×
src3, src1 + src2
01
src3
×
src1, src4 + src2
10
src1
×
src2, src3 + src4
11
src3
×
src1, src2 + src4
Version 5.0 or later
P
srcA
srcB srcD
srcC
00
src3
×
src4, src1 + src2
01
src3
×
src1, src4 + src2