Texas Instruments TMS320C3x 사용자 설명서

 Parallel MPYF3 and STF

13-153

  Assembly Language Instructions

src2, src1, dst  

||

STF 

src3, dst2

src1 

×

 src2 

→

 dst1

||

src3 

→

 dst2

src1

register (R

n1, 0 

≤

 

n1 

≤

 7)

src2

indirect (

disp = 0, 1, IR0, IR1)

dst1

register (R

n3, 0 

≤

 

n3 

≤

 7)

src3

register (R

n4, 0 

≤

 

n4 

≤

7)

dst2

indirect (

disp = 0, 1, IR0, IR1)

This instruction’s operands have been augmented in the following devices:

-

’C31 silicon revision 6.0 or greater

-

’C32 silicon revision 2.0 or greater

src1

register (R

n1, 0 

≤

 

n1 

≤

 7)

src2

indirect (

disp = 0, 1, IR0, IR1) or any CPU register

dst1

register (R

n2, 0 

≤

 

n2 

≤

 7)

src3

register (R

n3, 0 

≤

 

n3 

≤

 7)

dst2

indirect (

disp = 0, 1, IR0, IR1)

31

24 23

16

8 7

0

15

1 1

0 1 1 1

dst

1

src

2

dst

2

1

src

1

src

3

A floating-point multiplication and a floating-point store are performed in paral-
lel. All registers are read at the beginning and loaded at the end of the execute
cycle. If one of the parallel operations (MPYF3) writes to a register and the op-
eration being performed in parallel (STF) reads from the same register, then
STF accepts the contents of the register as input before it is modified by the
MPYF3.

If 

src2 and dst2 point to the same location, src2 is read before the write to dst2.

1