Texas Instruments TMS320C3x 사용자 설명서

Bitwise-Logical Complement

13-184

 

  src, dst

∼

src 

→

 

dst

src general addressing modes (G):

0 0

any CPU register

0 1

direct

1 0

indirect (disp = 0–255, IR0, IR1)

1 1

immediate

dst any CPU register

31

24 23

16

8 7

0

15

0 0 0

0 1

1

0

1

1

dst

src

G

The bitwise-logical complement of the 

src operand is loaded into the dst regis-

ter. The complement is formed by a logical NOT of each bit of the 

src operand.

The 

dst and src operands are assumed to be unsigned integers.

1

These condition flags are modified only if the destination register is R7 – R0.

Unaffected

Unaffected

0

MSB of the output

1 if a 0 result is generated; 0 otherwise

0

Unaffected

Operation is affected by OVM bit value.