Texas Instruments TMS320C3x 사용자 설명서
CPU Multiport Register File
3-3
CPU Registers
The registers also have some special functions for which they are particularly
appropriate. For example, the eight extended-precision registers are especially
suited for maintaining extended-precision floating-point results. The eight auxiliary
registers support a variety of indirect addressing modes and can be used as
general-purpose 32-bit integer and logical registers. The remaining registers
provide system functions, such as addressing, stack management, processor
status, interrupts, and block repeat. See Chapter 6,
appropriate. For example, the eight extended-precision registers are especially
suited for maintaining extended-precision floating-point results. The eight auxiliary
registers support a variety of indirect addressing modes and can be used as
general-purpose 32-bit integer and logical registers. The remaining registers
provide system functions, such as addressing, stack management, processor
status, interrupts, and block repeat. See Chapter 6,
Addressing Modes, for more
information.
3.1.1
Extended-Precision Registers (R7–R0)
The eight extended-precision registers (R7–R0) can store and support operations
on 32-bit integer and 40-bit floating-point numbers. These registers consist of two
separate and distinct regions:
on 32-bit integer and 40-bit floating-point numbers. These registers consist of two
separate and distinct regions:
-
Bits 39–32: dedicated to storage of the exponent (e) of the floating-point
number.
number.
-
Bits 31–0: store the mantissa of the floating-point number:
J
Bit 31: sign bit (s)
J
Bits 30–0: the fraction (f)
Any instruction that assumes the operands are floating-point numbers uses
bits 39–0. Figure 3–1 illustrates the storage of 40-bit floating-point numbers
in the extended-precision registers.
bits 39–0. Figure 3–1 illustrates the storage of 40-bit floating-point numbers
in the extended-precision registers.
Figure 3–1. Extended-Precision Register Floating-Point Format
Fraction
Sign
Exponent
39
32 31
30
0
Mantissa
For integer operations, bits 31–0 of the extended-precision registers contain
the integer (signed or unsigned). Any instruction that assumes the operands
are either signed or unsigned integers uses only bits 31–0. Bits 39–32 remain
unchanged. This is true for all shift operations. The storage of 32-bit integers
in the extended-precision registers is shown in Figure 3–2.
the integer (signed or unsigned). Any instruction that assumes the operands
are either signed or unsigned integers uses only bits 31–0. Bits 39–32 remain
unchanged. This is true for all shift operations. The storage of 32-bit integers
in the extended-precision registers is shown in Figure 3–2.
Figure 3–2. Extended-Precision Register Integer Format
Signed or unsigned integer
Unchanged
39
32 31
0