Texas Instruments TMS320C3x 사용자 설명서

Round Floating-Point Value

13-202

 

RND 

 src, dst

rnd(

src) 

→

 

dst

src general addressing modes (G):

0 0

register (R

n, 0 

≤

 

n 

≤

 7)

0 1

direct

1 0

indirect (disp = 0–255, IR0, IR1)

1 1

immediate

dst register (Rn, 0 

≤

n 

≤

 7)

31

24 23

16

8 7

0

15

0 0 0

1 0

1

0

0

0

dst

src

G

The result of rounding the

 src operand is loaded into the dst register.The src

operand is rounded to the nearest single-precision floating-point value. If the
src operand is exactly halfway between two single-precision values, it is
rounded to the most positive value.

1

These condition flags are modified only if the destination register is R7 – R0.

1 if a floating-point underflow occurs; unchanged otherwise

1 if a floating-point overflow occurs; unchanged otherwise

1 if a floating-point underflow occurs or the 

src operand is 0;

0 otherwise

1 if a negative result is generated; 0 otherwise

Unaffected

1 if a floating-point overflow occurs; 0 otherwise

Unaffected

Operation is affected by OVM bit value.