Texas Instruments TMS320C3x 사용자 설명서

 Store Floating-Point Value, Interlocked

13-215

  Assembly Language Instructions

STFI  

src, dst

src 

→

 dst

Signal end of interlocked operation.

src register (Rn, 0 

≤

 

n 

≤

 7)

dst general addressing modes (G):

0 1

direct

1 0

indirect (disp = 0–255, IR0, IR1)

31

24 23

16

8 7

0

15

0 0 0

1 0

0

0

1

1

src

G

dst

The 

src register is loaded into the dst memory location. An interlocked opera-

tion is signaled over pins XF0 and XF1. The 

src and dst operands are assumed

to be floating-point numbers. Refer to Section 7.4, 

Interlocked Operations, on

page 7-13 for detailed information.

1

LUF  

Unaffected

LV   

Unaffected

UF   

Unaffected

N Unaffected
Z    

Unaffected

V    

Unaffected

C    

Unaffected

Operation is not affected by OVM bit value.

STFI  R3,*–AR4

R3

07

 

33C0 0000

R3

07 33C0 0000

AR4

80 993C

AR4

80 993C

LUF

0

LUF

0

LV

0

LV

0

UF

0

UF

0

N

0

N

0

Z

0

Z

0

V

0

V

0

C

0

C

0

Data memory

80993Bh

0

80993Bh

733C000

1.79750e+02

1.79750e+02

1.79750e+02