Texas Instruments TMS320C3x 사용자 설명서
Store Integer
STI
13-219
Assembly Language Instructions
Syntax
STI
src, dst
Operation
src
→
dst
Operands
src register (Rn, 0
≤
n
≤
27)
dst general addressing modes (G):
0 1
direct
1 0
indirect (disp = 0–255, IR0, IR1)
Opcode
31
24 23
16
8 7
0
15
0 0 0
1 0
1
0
0
1
src
G
dst
Description
The
src register is loaded into the dst memory location. The src and dst oper-
ands are assumed to be signed integers.
Cycles
1
Status Bits
LUF
Unaffected
LV
Unaffected
UF
Unaffected
N
Unaffected
Z
Unaffected
V
Unaffected
C
Unaffected
OVM
Operation is not affected by OVM bit value.
Example
STI R4,@982Bh
Before Instruction
After Instruction
R4
00
0004 2BD7
R4
00 0004 2BD7
DP
080
DP
080
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
Data memory
80982Bh
0E5FC
80982Bh
42BD7
58,876
273,367
273,367
273,367
Mode Bit