Texas Instruments TMS320C3x 사용자 설명서

Subtract Integer Conditionally

13-226

 

SUBC 

 src, dst

If (

dst – src 

≥

 0):

(

dst – src << 1) OR 1 

→

 dst

Else:

dst << 1 

→

 dst

src general addressing modes (G):

0 0

register (R

n, 0 

≤

 

n 

≤

 27)

0 1

direct

1 0

indirect (disp = 0–255, IR0, IR1)

1 1

immediate

dst register (Rn, 0 

≤

 

n 

≤

 27)

31

24 23

16

8 7

0

15

0 0 0

1 0

1

1

0

1

dst

G

src

The

 src operand is subtracted from the dst operand. The dst operand is loaded

with a value dependent on the result of the subtraction. If (

dst – src) is greater

than or equal to 0, then (

dst – src) is left-shifted one bit, the least significant

bit is set to 1, and the result is loaded into the 

dst register. If (dst – src) is less

than 0, 

dst is left-shifted one bit and loaded into the dst register. The dst and

src operands are assumed to be unsigned integers.

You can use SUBC to perform a single step of a multi-bit integer division. See
the 

TMS320C3x General Purpose Applications Guide for a detailed descrip-

tion.

1

Unaffected

Unaffected

Unaffected

Unaffected

Unaffected

Unaffected

Unaffected

Operation is not affected by OVM bit value.