Texas Instruments TMS320C3x 사용자 설명서
SUBRF
Subtract Reverse Floating-Point Value
13-240
Syntax
SUBRF
src, dst
Operation
src – dst
→
dst
Operands
src general addressing modes (G):
0 0
register (R
n, 0
≤
n
≤
7)
0 1
direct
1 0
indirect (disp = 0–255, IR0, IR1)
1 1
immediate
dst register (Rn, 0
≤
n
≤
7)
Opcode
31
24 23
16
8 7
0
15
0 0 0
1 1
1
0
0
0
dst
G
src
Description
The difference between the
src operand and the dst operand is loaded into the
dst register. The dst and src operands are assumed to be floating-point num-
bers.
bers.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 – R0.
LUF
1 if a floating-point underflow occurs; unchanged otherwise
LV
1 if a floating-point overflow occurs; unchanged otherwise
UF
1 if a floating-point underflow occurs; 0 otherwise
N
1 if a negative result is generated; 0 otherwise
Z
1 if a 0 result is generated; 0 otherwise
V
1 if a floating-point overflow occurs; 0 otherwise
C
Unaffected
OVM
Operation is not affected by OVM bit value.
Example
SUBRF @9905h,R5
Before Instruction
After Instruction
R5
05 7B40 0000
R5
06 69E0 0000
DP
080
DP
080
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
Data memory
809905h
733C000
809905h
733C000
1.79750e+02
6.281250e+01
1.16937500e+02
1.79750e+02
Mode Bit