Texas Instruments TMS320C3x 사용자 설명서
Memory
4-7
Memory and the Instruction Cache
4.1.1.3
TMS320C32 Memory Map
The memory map depends on whether the processor is running in micropro-
cessor mode (MCBL/MP = 0) or microcomputer mode (MCBL/MP = 1). The
memory maps for these modes are similar (see Figure 4–3 on page 4-8).
Locations 800000h–807FFFh, 809800h–80FFFh, and 830000H–87FDFFh are
reserved. Locations 810000h–82FFFFh are mapped to the external bus with
IOSTRB active. All of the memory-mapped peripheral bus registers are in loca-
tions 808000h–8097FFh. In both modes, RAM block 0 is located at addresses
87FE00h–87FEFFh, and RAM block 1 is located at addresses 87FF00h–
87FFFFh. Locations 900000h–FFFFFFh are mapped to the external bus with
STRB1 active.
cessor mode (MCBL/MP = 0) or microcomputer mode (MCBL/MP = 1). The
memory maps for these modes are similar (see Figure 4–3 on page 4-8).
Locations 800000h–807FFFh, 809800h–80FFFh, and 830000H–87FDFFh are
reserved. Locations 810000h–82FFFFh are mapped to the external bus with
IOSTRB active. All of the memory-mapped peripheral bus registers are in loca-
tions 808000h–8097FFh. In both modes, RAM block 0 is located at addresses
87FE00h–87FEFFh, and RAM block 1 is located at addresses 87FF00h–
87FFFFh. Locations 900000h–FFFFFFh are mapped to the external bus with
STRB1 active.
Unlike the fixed interrupt-trap vector table location of the ’C30 and ’C31 devices,
the ’C32 has a user-relocatable interrupt-trap vector table. The interrupt-trap
vector table must start on a 256-word boundary. The starting location is pro-
grammed through the interrupt-trap table pointer (ITTP) bit field in the CPU inter-
rupt flag (IF) register. See Section 3.1.9.1,
the ’C32 has a user-relocatable interrupt-trap vector table. The interrupt-trap
vector table must start on a 256-word boundary. The starting location is pro-
grammed through the interrupt-trap table pointer (ITTP) bit field in the CPU inter-
rupt flag (IF) register. See Section 3.1.9.1,
Interrupt-Trap Table Pointer (ITTP),
on page 3-14.
-
Microprocessor Mode
In microprocessor mode, the boot loader is not mapped into the ’C3x memory
map. Locations 0h–7FFFFFFh are accessed over the external memory port
(STRB0 active) with location 0h containing the reset vector.
map. Locations 0h–7FFFFFFh are accessed over the external memory port
(STRB0 active) with location 0h containing the reset vector.
-
Microcomputer Mode
In microcomputer mode, the on-chip boot loader ROM is mapped into
locations 0h–0FFFh. Locations 1000h–7FFFFFh are accessed over the
external memory port (STRB0 active).
locations 0h–0FFFh. Locations 1000h–7FFFFFh are accessed over the
external memory port (STRB0 active).
The ’C32 boot loader has additional modes over the ’C31 boot loader to handle
the data types, sizes, and memory widths supported by the external memory inter-
face. The memory boot load supports data transfer with and without handshaking.
The handshake mode allows synchronous program transfer by using two pins as
data-acknowledge and data-ready signals.
the data types, sizes, and memory widths supported by the external memory inter-
face. The memory boot load supports data transfer with and without handshaking.
The handshake mode allows synchronous program transfer by using two pins as
data-acknowledge and data-ready signals.
See Section 4.1.2,
Peripheral Bus Memory Map, on page 4-9 and Section 4.2,
Reset/Interrupt/Trap Vector Map, on page 4-14 for more information.
Be careful! Access to a reserved area produces unpredictable
results.
results.