Texas Instruments VLYNQ Port 사용자 설명서

Address

translation

commands

Outbound

Outbound
command

FIFO

data

Return

FIFO

data

FIFO

Return

command

Inbound

FIFO

Registers

translation

Address

TxSM

8B/10B

encoding

Serializer

commands

Inbound

RxSM

Deserializer

decoding

8B/10B

Serial
TxData

Serial
RxData

System clock

Address

translation

Registers

commands

Inbound

translation

Address

commands

Outbound

8B/10B

decoding

FIFO

FIFO

command

Inbound

data

Return

FIFO

RxSM

Deserializer

RxData

Serial

encoding

8B/10B

VLYNQ Clock

command

Return

data

FIFO

Outbound

TxSM

Serializer

TxData

Serial

Slave

config bus

interface

System clock

VLYNQ clock

Local VLYNQ

Remote VLYNQ

Master

config bus

interface

Master

config bus

interface

Slave

config bus

interface

Write requests that initiate from the slave configuration bus interface of the local device write to the
outbound command (CMD) FIFO. Data is subsequently read from the FIFO and encapsulated in a write
request packet. The address is translated, and the packet is encoded and serialized before being
transmitted to remote device. The remote device subsequently deserializes and decodes the receive data
and writes it into the inbound CMD FIFO. A write operation initiates on the remote device’s master
configuration bus interface after reading the address and data from the FIFO.

The data flow between two VLYNQs that are connected is shown in

. In the example shown in

, the write originates from the DM644x device.

14

SPRUE36A – September 2007