Texas Instruments VLYNQ Port 사용자 설명서

www.ti.com

VLYNQ Port Registers

VLYNQ Port Registers

Table 5

describes the address space for the VLYNQ registers and memory.

Table 5. VLYNQ Register Address Space

Block Name

Start Address

End Address

Size

VLYNQ Control Registers

01E0 1000h

01E0 11FFh

512 bytes

Reserved

01E0 1200h

01E0 1FFFh

VLYNQ Remote Memory Map

0C00 0000h

0CFF FFFFh

64 Mbytes

Table 6

lists the memory-mapped registers for the VLYNQ port controller. See the device-specific data

manual for the memory address of these registers.

The first 128 bytes map to the VLYNQ configuration registers that are maintained by the local (device)
VLYNQ register control module while the second 128 bytes map to the remote configuration registers that
are physically located in the remote device linked by the VLYNQ serial interface. Any access to the
second set of registers causes VLYNQ to issue a read or write VLYNQ packet to be transmitted and only
completes if a link is established between the two devices.

Table 6. VLYNQ Port Controller Registers

Offset

Acronym

Register Description

Section

REVID

Revision Register

Section 3.1

CTRL

Control Register

Section 3.2

STAT