Texas Instruments VLYNQ Port 사용자 설명서
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3.6
Interrupt Pending/Set Register (INTPENDSET)
3.7
Interrupt Pointer Register (INTPTR)
VLYNQ Port Registers
The interrupt pending/set register (INTPENDSET) indicates the pending interrupt status when the
INTLOCAL bit in the control register (CTRL) is not set. When the interrupt packet is forwarded on the
serial interface, these bits are cleared. The INTPENDSET is shown in
INTLOCAL bit in the control register (CTRL) is not set. When the interrupt packet is forwarded on the
serial interface, these bits are cleared. The INTPENDSET is shown in
and described in
.
Figure 14. Interrupt Pending/Set Register (INTPENDSET)
31
0
INTSET
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 12. Interrupt Pending/Set Register (INTPENDSET) Field Descriptions
Bit
Field
Value
Description
31-0
INTSET
0-FFFF FFFFh
This field indicates the unmasked status of each pending interrupt.
0
Writing a 0 has no effect.
1
Writing a 1 to any bit:
if INTLOCAL = 0 in CTRL, interrupt packet is sent on the serial interface.
If INTLOCAL = 1 in CTRL, VLYNQ module interrupt (VLQINT) is asserted.
The interrupt pointer register (INTPTR) typically contains the address of the interrupt pending/set register
(INTPENDSET) within the VLYNQ module. To program INTPTR to point to INTPENDSET, program a
value of 14h (the offset of INTPENDSET). Additionally, the INT2CFG bit in the control register (CTRL)
should be set to 1. The INTPTR is shown in
(INTPENDSET) within the VLYNQ module. To program INTPTR to point to INTPENDSET, program a
value of 14h (the offset of INTPENDSET). Additionally, the INT2CFG bit in the control register (CTRL)
should be set to 1. The INTPTR is shown in
and described in
.
Figure 15. Interrupt Pointer Register (INTPTR)
31
2
1
0
INTPTR
Reserved
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13. Interrupt Pointer Register (INTPTR) Field Descriptions
Bit
Field
Value
Description
31-2
INTPTR
0-3FFF FFFFh
Interrupt pointer. Program this register with the address of the interrupt pending/set register
(14h).
(14h).
1-0
Reserved
0
Reserved. Always read as 0. Writes have no effect.
32
VLYNQ Port
SPRUE36A – September 2007