Nortel Networks MSC8101 ADS 사용자 설명서

18

MOTOROLA

Hardware Preparation

The internal Logic & PLL’s of the MSC8101 is powered separately through a supply bus named
1V5. The voltage level over this power bus may vary between 0.9V - 2.1V. In the lower voltage
level, the Processor will operate at lower frequency range, consuming a smaller amount of power
and vice-versa for the higher voltage level.
1V5 power level is factory set for 1.5V, but may be changed by RP2.

During Power On reset sequence the Processor samples the three MODCK(1:3) lines which are
driven by Altera FPGA device in accordance with SW9/1-3 setting. MODCK_HI field (MODCK[4–
6]), taken from the reset configuration word, are read from the Flash memory (default value from
Altera FPGA for non-programmed Flash is read from SW9/4-6) or from Host Interface to establish
with the multiplication factors of the CPM’s and Core’s PLLs. SW9 is shown in 

Some Clock Configuration can see in 

The HReset Configuration Word

A

, read by the Processor while HRESET~ is asserted, may be

taken from three sources:

1)

Flash Memory SIMM.

2)

Altera FPGA (Safe Mode).

3)

Host I/F.

When SW9/7 is OFF, the Hard Reset Configuration Word is taken from Altera FPGA, when it is
ON, the Hard Reset Configuration Word is taken from the Flash SIMM. If SW9/8 (Configuration)
set OFF the Processor will be configured from Host, independent of SW9/7 (Flash Configuration
Enable) position. For correct operation for Host Config. Mode Data bus width will be set to 32-bit
wide.

A. In fact 8 Hard-Reset configuration words are read by a configuration master, however only the first is rel-

evant for a single MSC8101.

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Freescale Semiconductor, Inc.

For More Information On This Product,

   Go to: www.freescale.com

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