Nxp Semiconductors UM10237 사용자 설명서
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
761 of 792
NXP Semiconductors
UM10237
Chapter 36: LPC24XX Supplementary information
3.
Tables
Table 10. LPC2470 ordering options . . . . . . . . . . . . . . . . .8
Table 11. LPC2478 ordering information . . . . . . . . . . . . . .8
Table 12. LPC2478 ordering options . . . . . . . . . . . . . . . . .8
Table 13. LPC2400 memory options and addressing. . . .16
Table 14. LPC2458 memory usage and details . . . . . . . .16
Table 15. LPC2420/60/70 memory usage and details . . .17
Table 16. LPC2468/78 memory usage and details. . . . . .17
Table 17. APB peripherals and base addresses . . . . . . .22
Table 18. ARM exception vector locations . . . . . . . . . . . .23
Table 19. LPC2400 Memory mapping modes . . . . . . . . .24
Table 20. Memory mapping control registers . . . . . . . . . .25
Table 21. Memory Mapping control register (MEMMAP -
Table 11. LPC2478 ordering information . . . . . . . . . . . . . .8
Table 12. LPC2478 ordering options . . . . . . . . . . . . . . . . .8
Table 13. LPC2400 memory options and addressing. . . .16
Table 14. LPC2458 memory usage and details . . . . . . . .16
Table 15. LPC2420/60/70 memory usage and details . . .17
Table 16. LPC2468/78 memory usage and details. . . . . .17
Table 17. APB peripherals and base addresses . . . . . . .22
Table 18. ARM exception vector locations . . . . . . . . . . . .23
Table 19. LPC2400 Memory mapping modes . . . . . . . . .24
Table 20. Memory mapping control registers . . . . . . . . . .25
Table 21. Memory Mapping control register (MEMMAP -
Table 22. Pin summary. . . . . . . . . . . . . . . . . . . . . . . . . . .28
Table 23. Summary of system control registers . . . . . . . .28
Table 24. External Interrupt registers . . . . . . . . . . . . . . . .29
Table 25. External Interrupt Flag register (EXTINT - address
Table 23. Summary of system control registers . . . . . . . .28
Table 24. External Interrupt registers . . . . . . . . . . . . . . . .29
Table 25. External Interrupt Flag register (EXTINT - address
Table 30. AHB configuration register map . . . . . . . . . . . .36
Table 31. AHB Arbiter Configuration register 1 (AHBCFG1 -
Table 31. AHB Arbiter Configuration register 1 (AHBCFG1 -
Table 37. Priority sequence (bit 0 = 0): Ethernet, CPU . .39
Table 38. Priority sequence (bit 0 = 0): Ethernet, CPU . .40
Table 39. Recommended values for C
Table 38. Priority sequence (bit 0 = 0): Ethernet, CPU . .40
Table 39. Recommended values for C
X1/X2
in oscillation
mode (crystal and external components
parameters) low frequency mode (OSCRANGE =
0, see
parameters) low frequency mode (OSCRANGE =
0, see
Table 3–29
) . . . . . . . . . . . . . . . . . . . . . .44
X1/X2
in oscillation
mode (crystal and external components
parameters) high frequency mode (OSCRANGE =
1, see
1, see
Table 3–29
) . . . . . . . . . . . . . . . . . . . . . . 44
Table 41. Summary of system control registers. . . . . . . . 45
Table 42. Clock Source Select register (CLKSRCSEL -
Table 42. Clock Source Select register (CLKSRCSEL -
Table 46. Multiplier values for a 32 kHz oscillator . . . . . . 49
Table 47. PLL Status register (PLLSTAT - address
Table 47. PLL Status register (PLLSTAT - address
Table 52. Potential values for PLL example . . . . . . . . . . 55
Table 53. CPU Clock Configuration register (CCLKCFG -
Table 53. CPU Clock Configuration register (CCLKCFG -
Table 58. Peripheral Clock Selection register bit values . 59
Table 59. Power Control registers . . . . . . . . . . . . . . . . . . 61
Table 60. Power Mode Control register (PCON - address
Table 59. Power Control registers . . . . . . . . . . . . . . . . . . 61
Table 60. Power Mode Control register (PCON - address
Table 61. Encoding of reduced power modes . . . . . . . . . 62
Table 62. Interrupt Wakeup register (INTWAKE - address
Table 62. Interrupt Wakeup register (INTWAKE - address
Table 64. EMC configuration . . . . . . . . . . . . . . . . . . . . . . 67
Table 65. Memory bank selection . . . . . . . . . . . . . . . . . . 72
Table 66. Pad interface and control signal descriptions . 73
Table 67. Summary of EMC registers . . . . . . . . . . . . . . . 74
Table 68. EMC Control register (EMCControl - address
Table 65. Memory bank selection . . . . . . . . . . . . . . . . . . 72
Table 66. Pad interface and control signal descriptions . 73
Table 67. Summary of EMC registers . . . . . . . . . . . . . . . 74
Table 68. EMC Control register (EMCControl - address