Emerson CC1000DM 사용자 설명서
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P M C / P C I I N T E R F A C E
PCI Bus Control Signals
3-13
INTA*, INTB*, INTC*, INTD*:
PMC INTERRUPTS A, B, C, D lines are used to interrupt the CPU.
IRDY*:
INITIATOR READY sustained tri-state signal indicates that the bus master is ready to
complete the data phase of the transaction.
complete the data phase of the transaction.
LOCK*:
LOCK sustained tri-state signal indicates an atomic operation to a bridge that may
require multiple transactions to complete.
require multiple transactions to complete.
M66EN:
66 MHZ ENABLE input pin indicates to a device whether the bus segment is operating
at 66 or 33 MHz.
at 66 or 33 MHz.
MONARCH:
MONARCH when grounded, indicates that the PrPMC module is a Monarch and must
provide PCI bus enumeration and interrupt handling.
provide PCI bus enumeration and interrupt handling.
PAR:
PARITY is even parity across AD00-AD31 and C/BE0-C/BE3*. Parity generation is
required by all PCI agents. This tri-state signal is stable and valid one clock after the
address phase, and one clock after the bus master indicates that it is ready to complete
the data phase (either IRDY* or TRDY* is asserted). Once PAR is asserted, it remains
valid until one clock after the completion of the current data phase.
required by all PCI agents. This tri-state signal is stable and valid one clock after the
address phase, and one clock after the bus master indicates that it is ready to complete
the data phase (either IRDY* or TRDY* is asserted). Once PAR is asserted, it remains
valid until one clock after the completion of the current data phase.
PAR64:
PARITY UPPER DWORD tri-state signal is even parity that protects AD[63:0] and
C/BE[7:0]*. PAR64 must be valid one clock after each address phase on any transaction
in which REQ64* is asserted.
C/BE[7:0]*. PAR64 must be valid one clock after each address phase on any transaction
in which REQ64* is asserted.
PERR*:
PARITY ERROR sustained tri-state line is used to report parity errors during all PCI
transactions.
transactions.
PME*:
Power Management Event optional open-drain signal (pull-up resistor required) allows
a device to request a change in the power state. Devices must be enabled by software
before asserting this signal.
a device to request a change in the power state. Devices must be enabled by software
before asserting this signal.
REQ*:
REQUEST output pin indicates to the arbiter that a particular master wants to use the
bus.
bus.
RST*:
RESET; assertion of this input line brings PCI registers, sequencers, and signals to a
consistent state.
consistent state.
SERR*:
SYSTEMS ERROR open-collector output signal is used to report any system error with
catastrophic results.
catastrophic results.
STOP*:
STOP is a sustained tri-state signal used by the current target to request that the bus
master stop the current transaction.
master stop the current transaction.
TDI*:
TEST DATA INPUT signal serially shifts test data and test instructions into the device
during test access port (TAP) operation.
during test access port (TAP) operation.
TDO*:
TEST DATA OUTPUT signal serially shifts test data and test instructions out of the
device during TAP operation.
device during TAP operation.
TMS*:
TEST MODE SELECT input signal controls the state of the TAP controller in the device.