Jameco Electronics 3000 사용자 설명서
180
Rabbit 3000 Microprocessor
12.4 Transmit Serial Data Timing
On transmit, if the interrupts are enabled, an interrupt is requested when the transmit regis-
ter becomes empty and, in addition, an interrupt occurs when the shift register and trans-
mit register both become empty, that is, when the transmitter becomes idle. The shift
register is empty when the last bit is shifted out. When the transmit data register contains
data and the shift register finishes sending data, the data bits are clocked from the transmit
register to the shift register, and the shift register is never idle. The interrupt request is
cleared either by writing to the data register or by writing to the status register (which does
not affect the status register). The data register normally is clocked into the shift register
each time the shift register finishes sending data, leaving the data register empty. This
causes an interrupt request. The interrupt routine normally answers the interrupt before
the shift register runs dry (9 to 11 baud clocks, depending on the mode of operation). The
interrupt routine stores the next data item in the data register, clearing the interrupt request
and supplying the next data bits to be sent. When all the characters have been sent, the
interrupt service routine answers the interrupt once the data register becomes empty.
Since it has no more data, it clears the interrupt request by storing to the status register. At
this point the routine should check if the shift register is empty; normally it won’t be. If it
is, because the interrupt was answered late, the interrupt routine should do any final
cleanup and store to the status register again in case the shift register became empty after
the pending interrupt is cleared. Normally, though, the interrupt service routine will return
and there will be a final interrupt to give the routine a chance to disable the output buffers,
as in the case for RS-485 transmission.
ter becomes empty and, in addition, an interrupt occurs when the shift register and trans-
mit register both become empty, that is, when the transmitter becomes idle. The shift
register is empty when the last bit is shifted out. When the transmit data register contains
data and the shift register finishes sending data, the data bits are clocked from the transmit
register to the shift register, and the shift register is never idle. The interrupt request is
cleared either by writing to the data register or by writing to the status register (which does
not affect the status register). The data register normally is clocked into the shift register
each time the shift register finishes sending data, leaving the data register empty. This
causes an interrupt request. The interrupt routine normally answers the interrupt before
the shift register runs dry (9 to 11 baud clocks, depending on the mode of operation). The
interrupt routine stores the next data item in the data register, clearing the interrupt request
and supplying the next data bits to be sent. When all the characters have been sent, the
interrupt service routine answers the interrupt once the data register becomes empty.
Since it has no more data, it clears the interrupt request by storing to the status register. At
this point the routine should check if the shift register is empty; normally it won’t be. If it
is, because the interrupt was answered late, the interrupt routine should do any final
cleanup and store to the status register again in case the shift register became empty after
the pending interrupt is cleared. Normally, though, the interrupt service routine will return
and there will be a final interrupt to give the routine a chance to disable the output buffers,
as in the case for RS-485 transmission.