Motorola MCF5281 사용자 설명서

3-8

MOTOROLA

 

Table 3-2 summarizes the interaction of the MACSR[S/U,F/I,R/T] control bits.

This section describes behavior when the fractional mode is used (MACSR[F/I] is set).

When the processor is in fractional mode, there are two operations during which rounding
can occur.

• Execution of a store accumulator instruction (MOV.L ACCx,Rx). The lsbs of the 

48-bit accumulator logic are used to round the resulting 16- or 32-bit value. If 
MACSR[S/U] is cleared, the low-order 8 bits are used to round the resulting 32-bit 
fraction. If MACSR[S/U] is set, the low-order 24 bits are used to round the resulting 
16-bit fraction.

2

Z

Zero. Set if the result equals zero, otherwise cleared. This bit is affected only by MAC, MSAC, and 
load operations; it is not affected by MULS and MULU instructions.

1

V

Overflow. Set if an arithmetic overflow occurs on a MAC or MSAC instruction indicating that the 
result cannot be represented in the limited width of the EMAC. V is set only if a product overflow 
occurs or the accumulation overflows the 48-bit structure. V is evaluated on each MAC or MSAC 
operation and uses the appropriate PAVx flag in the next-state V evaluation.

0

EV

Extension overflow. Signals that the last MAC or MSAC instruction overflowed the 32 lsbs in 
integer mode or the 40 lsbs in fractional mode of the destination accumulator. However, the result is 
still accurately represented in the combined 48-bit accumulator structure. Although an overflow has 
occurred, the correct result, sign, and magnitude are contained in the 48-bit accumulator. Subsequent 
MAC or MSAC operations may return the accumulator to a valid 32/40-bit result.

0

0

x

Signed, integer

0

1

0

Signed, fractional
Truncate on MAC.L and MSAC.L
No round on accumulator stores

0

1

1

Signed, fractional
Round on MAC.L and MSAC.L
Round-to-32-bits on accumulator stores

1

0

x

Unsigned, integer

1

1

0

Signed, fractional
Truncate on MAC.L and MSAC.L
Round-to-16-bits on accumulator stores

1

1

1

Signed, fractional
Round on MAC.L and MSAC.L
Round-to-16-bits on accumulator stores