Motorola MCF5281 사용자 설명서
MOTOROLA
Chapter 4. Cache
4-7
Cache Programming Model
4.4
Cache Programming Model
Three supervisor registers define the operation of the cache and local bus controller: the
cache control register (CACR) and two access control registers (ACR0, ACR1).
cache control register (CACR) and two access control registers (ACR0, ACR1).
4.4.1
Cache Registers Memory Map
Table 4-3 below shows the memory map of the cache and access control registers.
The following lists several keynotes regarding the programming model table:
• The CACR and ACRs can only be accessed in supervisor mode using the MOVEC
instruction with an Rc value of 0x002, 0x004 and 0x005, respectively.
• Addresses not assigned to the registers and undefined register bits are reserved for
future expansion. Write accesses to these reserved address spaces and reserved
register bits have no effect, and read accesses will return zeros.
register bits have no effect, and read accesses will return zeros.
• The reset value column indicates the register initial value at reset. Certain registers
may be uninitialized upon reset; that is, they may contain random values after reset.
• The access column indicates if the corresponding register allows both read/write
functionality (R/W), read-only functionality (R), or write-only functionality (W). If
a read access to a write-only register is attempted, zeros will be returned. If a write
access to a read-only register is attempted, the access will be ignored and no write
will occur.
a read access to a write-only register is attempted, zeros will be returned. If a write
access to a read-only register is attempted, the access will be ignored and no write
will occur.
4.4.2
Cache Registers
4.4.2.1
Cache Control Register (CACR)
The CACR controls the operation of the cache. The CACR provides a set of default
memory access attributes used when a reference address does not map into the spaces
defined by the ACRs.
memory access attributes used when a reference address does not map into the spaces
defined by the ACRs.
The CACR is a 32-bit write-only supervisor control register. It is accessed in the CPU
address space via the MOVEC instruction with an Rc encoding of 0x002. The CACR can
be read when in background debug mode (BDM). At system reset, the entire register is
cleared.
address space via the MOVEC instruction with an Rc encoding of 0x002. The CACR can
be read when in background debug mode (BDM). At system reset, the entire register is
cleared.
Table 4-3. Memory Map of Cache Registers
Address
Name
Width
Description
Reset Value
Access
MOVEC with 0x002
CACR
32
Cache Control Register
0x0000_0000
W
MOVEC with 0x004
ACR0
32
Access Control Register 0
0x0000_0000
W
MOVEC with 0x005
ACR1
32
Access Control Register 1
0x0000_0000
W