Motorola MCF5281 사용자 설명서
MOTOROLA
Chapter 7. Power Management
7-9
Functional Description
In stop mode, the UARTs stop immediately and freeze their operation, register values, state
machines, and external pins. During this mode, the UART clocks are shut down. Coming
out of stop mode returns the UARTs to operation from the state prior to the low-power mode
entry.
machines, and external pins. During this mode, the UART clocks are shut down. Coming
out of stop mode returns the UARTs to operation from the state prior to the low-power mode
entry.
7.3.2.9
I
2
C Module
When the I
2
C Module is enabled by the setting of the I2CR[IEN] bit and when the device
is not in stop mode, the I
2
C module is operable and may generate an interrupt to bring the
device out of a low-power mode. For an interrupt to occur, the I2CR[IIE] bit must be set to
enable interrupts, and the setting of the I2SR[IIF] generates the interrupt signal to the CPU
and interrupt controller. The setting of I2SR[IIF] signifies either the completion of one byte
transfer or the reception of a calling address matching its own specified address when in
slave receive mode.
enable interrupts, and the setting of the I2SR[IIF] generates the interrupt signal to the CPU
and interrupt controller. The setting of I2SR[IIF] signifies either the completion of one byte
transfer or the reception of a calling address matching its own specified address when in
slave receive mode.
In stop mode, the I
2
C Module stops immediately and freezes operation, register values, and
external pins. Upon exiting stop mode, the I
2
C resumes operation unless stop mode was
exited by reset.
7.3.2.10 Queued Serial Peripheral Interface (QSPI)
In wait and doze modes, the queued serial peripheral interface (QSPI) may generate an
interrupt to exit the low-power modes.
interrupt to exit the low-power modes.
• Clearing the QSPI enable bit (SPE) disables the QSPI function.
• The QSPI is unaffected by wait mode and may generate an interrupt to exit this
• The QSPI is unaffected by wait mode and may generate an interrupt to exit this
mode.
In stop mode, the QSPI stops immediately and freezes operation, register values, state
machines, and external pins. During this mode, the QSPI clocks are shut down. Coming out
of stop mode returns the QSPI to operation from the state prior to the low-power mode
entry.
machines, and external pins. During this mode, the QSPI clocks are shut down. Coming out
of stop mode returns the QSPI to operation from the state prior to the low-power mode
entry.
7.3.2.11 DMA Timers (DMAT0–DMAT3)
In wait and doze modes, the DMA timers may generate an interrupt to exit a low-power
mode. This interrupt can be generated when the DMA Timer is in either input capture mode
or reference compare mode.
mode. This interrupt can be generated when the DMA Timer is in either input capture mode
or reference compare mode.
In input capture mode, where the capture enable (CE) field of the timer mode register
(DTMR) has a non-zero value and the DMA enable (DMAEN) bit of the DMA timer
extended mode register (DTXMR) is cleared, an interrupt is issued upon a captured input.
In reference compare mode, where the output reference request interrupt enable (ORRI) bit
of DTMR is set and the DTXMR[DMAEN] bit is cleared, an interrupt is issued when the
timer counter reaches the reference value.
(DTMR) has a non-zero value and the DMA enable (DMAEN) bit of the DMA timer
extended mode register (DTXMR) is cleared, an interrupt is issued upon a captured input.
In reference compare mode, where the output reference request interrupt enable (ORRI) bit
of DTMR is set and the DTXMR[DMAEN] bit is cleared, an interrupt is issued when the
timer counter reaches the reference value.