Motorola MCF5281 사용자 설명서

8-2

MOTOROLA

 

— Core reset status register (CRSR) indicates type of last reset
— Core watchdog control register (CWCR) for watchdog timer control
— Core watchdog service register (CWSR) to service watchdog timer

• System bus master arbitration programming model (MPARK)
• System access control unit (SACU) programming model

— Master privilege register (MPR)
— Peripheral access control registers (PACRs)
— Grouped peripheral access control registers (GPACR0, GPACR1)

The memory map for the SCM registers is shown in Table 8-1. All the registers in the SCM
are memory-mapped as offsets within the 1 Gbyte IPS address space and accesses are
controlled to these registers by the control definitions programmed into the SACU.

0x00_0000

IPSBAR

0x00_0004

—

0x00_0008

RAMBAR

0x00_000C

—

0x00_0010

CRSR

CWCR

LPICR

 1

1

The LPICR is described in Chapter 7, “Power Management."

CWSR

0x00_0018

—

0x00_001C

MPARK

0x00_0020

MPR

—

0x00_0024

PACR0

PACR1

PACR2

PACR3

0x00_0028

PACR4

—

PACR5

PACR6

0x00_002c

PACR7

—

PACR8

—

0x00_0030

GPACR0

GPACR1

—

—

0x00_0034

—

—

—

—

0x00_0038

—

—

—

—

0x00_003C

—

—

—

—