Motorola MCF5281 사용자 설명서

9-12

MOTOROLA

 

3. Write the MFD value from step 1 to the SYNCR.
4. Monitor the LOCK flag in SYNSR. When the PLL achieves lock, write the RFD 

value from step 1 to the RFD field of the SYNCR. This changes the system clocks 
frequency to the required frequency.

Keep the maximum system clock frequency below the limit
given in the Electrical Characteristics.

In PLL mode, the PLL synthesizes the system clocks. The PLL can multiply the reference
clock frequency by 2x to 9x, provided that the system clock frequency remains within the
range listed in electrical specifications. For example, if the reference frequency is 2 MHz,
the PLL can synthesize frequencies of 4 MHz to 18 MHz. In addition, the RFD can reduce
the system frequency by dividing the output of the PLL. The RFD is not in the feedback
loop of the PLL, so changing the RFD divisor does not affect PLL operation.

Figure 9-5 shows the external support circuitry for the crystal oscillator with example
component values. Actual component values depend on crystal specifications.

The following subsections describe each major block of the PLL. Refer to Figure  to see
how these functional sub-blocks interact.

The PFD is a dual-latch phase-frequency detector. It compares both the phase and
frequency of the reference and feedback clocks. The reference clock comes from either the
crystal oscillator or an external clock source. 

V

SS

V

SSSYN

EXTAL

XTAL

RS

RF

C1

C2

ON-CHIP

8-MHz CRYSTAL CONFIGURATIO

C1 = C2 = 16 pF

RF = 1 M

Ω

RS = 470 

Ω