Motorola MCF5281 사용자 설명서

10-10

MOTOROLA

 

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10.3.4 Interrupt Request Level Register (IRLRn)

This 7-bit register is updated each machine cycle and represents the current interrupt
requests for each interrupt level, where bit 7 corresponds to level 7, bit 6 to level 6, etc. This
register output is combined with similar outputs from INTC1 and eventually encoded into
the 3-bit priority interrupt level driven to the processor core.

31

16

Field

INTFRCL[31:16]

Reset

0000_0000_0000_0000

R/W

R

15

1

0

Field

INTFRCL[16:1]

—

Reset

0000_0000_0000_0000

R/W

R

IPSBAR + 0xC14, 0xD14

Figure 10-6. Interrupt Force Register Low (INTFRCLn)

Table 10-9. INTFRCLn Field Descriptions 

31–1

INTFRC Interrupt force. Allows software generation of interrupts for each possible source for functional or 

debug purposes.
0  No interrupt forced on corresponding interrupt source
1  Force an interrupt on the corresponding source

0

—

Reserved, should be cleared.

7

2

1

0

Field

IRQ[7:1]

—

Reset

0000_0000

R/W

R

Address

IPSBAR + 0xC18, 0xD18

Figure 10-7. Interrupt RequestLevel Register (IRLRn) 

Table 10-10. IRQn Field Descriptions 

7–1

IRQ

Interrupt requests. Represents the prioritized active interrupts for each level.
0  There are no active interrupts at this level
1  There is an active interrupt at this level

0

—

Reserved