Motorola MCF5281 사용자 설명서
MOTOROLA
Chapter 11. Edge Port Module (EPORT)
11-3
Memory Map and Registers
11.4 Memory Map and Registers
This subsection describes the memory map and register structure.
11.4.1 Memory Map
Refer to Table 11-2 for a description of the EPORT memory map. The EPORT has an
IPSBAR offset for base address of 0x0013_0000.
IPSBAR offset for base address of 0x0013_0000.
11.4.2 Registers
The EPORT programming model consists of these registers:
• The EPORT pin assignment register (EPPAR) controls the function of each pin
individually.
• The EPORT data direction register (EPDDR) controls the direction of each one of
the pins individually.
• The EPORT interrupt enable register (EPIER) enables interrupt requests for each pin
individually.
• The EPORT data register (EPDR) holds the data to be driven to the pins.
• The EPORT pin data register (EPPDR) reflects the current state of the pins.
• The EPORT flag register (EPFR) individually latches EPORT edge events.
• The EPORT pin data register (EPPDR) reflects the current state of the pins.
• The EPORT flag register (EPFR) individually latches EPORT edge events.
Table 11-2. Edge Port Module Memory Map
IPSBAR
Offset
Bits 15–8
Bits 7–0
Access
1
1
S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User mode accesses to supervisor only
addresses have no effect and result in a cycle termination transfer error.
addresses have no effect and result in a cycle termination transfer error.
0x0013_0000
EPORT Pin Assignment Register (EPPAR)
S
0x0013_0002
EPORT Data Direction Register (EPDDR)
EPORT Interrupt Enable Register (EPIER)
S
0x0013_0004
EPORT Data Register (EPDR)
EPORT Pin Data Register (EPPDR)
S/U
0x0013_0006
EPORT Flag Register (EPFR)
Reserved
2
2
Writing to reserved address locations has no effect, and reading returns 0s.
S/U