Motorola MCF5281 사용자 설명서
13-4
MCF5282 User’s Manual
MOTOROLA
Data Transfer Operation
(configured in CSCR0–CSCR7) and DRAM block 0 and 1 address and control registers
(configured in DACR0 and DACR1). If the driven address compares with one of the
programmed chip selects or DRAM blocks, the appropriate chip select is asserted or the
DRAM block is selected using the specifications programmed by the user in the respective
configuration register. Otherwise, the following occurs:
(configured in DACR0 and DACR1). If the driven address compares with one of the
programmed chip selects or DRAM blocks, the appropriate chip select is asserted or the
DRAM block is selected using the specifications programmed by the user in the respective
configuration register. Otherwise, the following occurs:
• If the address and attributes do not match in CSCR or DACR, the MCF5282 runs an
external burst-inhibited bus cycle with a default of external termination on a 32-bit
port.
port.
• Should an address and attribute match in multiple CSCRs, the matching chip-select
signals are driven; however, the MCF5282 runs an external burst-inhibited bus cycle
with external termination on a 32-bit port.
with external termination on a 32-bit port.
• Should an address and attribute match both DACRs or a DACR and a CSCR, the
operation is undefined.
Table 13-2 shows the type of access as a function of match in the CSCRs and DACRs.
Basic operation of the MCF5282 bus is a three-clock bus cycle.
1. During the first clock, the address, attributes, and TS are driven.
2. Data and TA are sampled during the second clock of a bus-read cycle. During a read,
2. Data and TA are sampled during the second clock of a bus-read cycle. During a read,
the external device provides data and is sampled at the rising edge at the end of the
second bus clock. This data is concurrent with TA, which is also sampled at the
rising edge of the clock.
During a write, the ColdFire device drives data from the rising clock edge at the end
of the first clock to the rising clock edge at the end of the bus cycle. Wait states can
be added between the first and second clocks by delaying the assertion of TA. TA
can be configured to be generated internally through the CSCRs. If TA is not
generated internally, the system must provide it externally.
second bus clock. This data is concurrent with TA, which is also sampled at the
rising edge of the clock.
During a write, the ColdFire device drives data from the rising clock edge at the end
of the first clock to the rising clock edge at the end of the bus cycle. Wait states can
be added between the first and second clocks by delaying the assertion of TA. TA
can be configured to be generated internally through the CSCRs. If TA is not
generated internally, the system must provide it externally.
Table 13-2. Accesses by Matches in CSCRs and DACRs
Number of CSCR Matches
Number of DACR Matches
Type of Access
0
0
External
1
0
Defined by CSCR
Multiple
0
External, burst-inhibited, 32-bit
0
1
Defined by DACRs
1
1
Undefined
Multiple
1
Undefined
0
Multiple
Undefined
1
Multiple
Undefined
Multiple
Multiple
Undefined