Motorola MCF5281 사용자 설명서
MOTOROLA
Chapter 16. DMA Controller Module
16-5
DMA Controller Module Programming Model
16.4 DMA Controller Module Programming Model
This section describes each internal register and its bit assignment. Note that modifying
DMA control registers during a DMA transfer can result in undefined operation. Table 16-2
shows the mapping of DMA controller registers. Note the differences for the byte count
registers depending on the value of MPARK[BCR24BIT]. See Section 8.5.3, “Bus Master
Park Register (MPARK)” for further information.
DMA control registers during a DMA transfer can result in undefined operation. Table 16-2
shows the mapping of DMA controller registers. Note the differences for the byte count
registers depending on the value of MPARK[BCR24BIT]. See Section 8.5.3, “Bus Master
Park Register (MPARK)” for further information.
Table 16-2. Memory Map for DMA Controller Module Registers
DMA
Channel
IPSBAR
Offset
[31:24]
[23:16]
[15:8]
[7:0]
0
0x100
Source address register 0 (SAR0) [p. 16-6]
0x104
Destination address register 0 (DAR0) [p. 16-6]
0x108
DMA control register 0 (DCR0) [p. 16-8]
0x10C
Byte count register 0 (BCR24BIT = 0)
1
1
The DMA module originally supported a left-justified 16-bit byte count register (BCR). This function was later reimplemented as
a right-justified 24-bit BCR. The operation of the DMA and the interpretation of the BCR is controlled by the
MPARK[BCR24BIT]. See Section 8.5.3, “Bus Master Park Register (MPARK)" for more details.
a right-justified 24-bit BCR. The operation of the DMA and the interpretation of the BCR is controlled by the
MPARK[BCR24BIT]. See Section 8.5.3, “Bus Master Park Register (MPARK)" for more details.
Reserved
0x10C
Reserved
0x110
DMA status register 0
Reserved
1
0x140
Source address register 1 (SAR1) [p. 16-6]
0x144
Destination address register 1 (DAR1) [p. 16-6]
0x148
DMA control register 1 (DCR1) [p. 16-8]
0x14C
Byte count register 1 (BCR24BIT = 0)
Reserved
0x14C
Reserved
0x150
DMA status register 1
Reserved
2
0x180
Source address register 2 (SAR2) [p. 16-6]
0x184
Destination address register 2 (DAR2) [p. 16-6]
0x188
DMA control register 2 (DCR2) [p. 16-8]
0x18C
Byte count register 2 (BCR24BIT = 0)
Reserved
0x18C
Reserved
0x190
DMA status register 2
Reserved
3
0x1C0
Source address register 3 (SAR3) [p. 16-6]
0x1C4
Destination address register 3 (DAR3) [p. 16-6]
0x1C8
DMA control register 3 (DCR3) [p. 16-8]
0x1CC
Byte count register 3 (BCR24BIT = 0)
Reserved
0x1CC
Reserved
Byte count register 3 (BCR24BIT = 1)
0x1D0
DMA status register 3
Reserved