Motorola MCF5281 사용자 설명서
17-16
MCF5282 User’s Manual
MOTOROLA
Functional Description
17.4.10 Full Duplex Flow Control
Full-duplex flow control allows the user to transmit pause frames and to detect received
pause frames. Upon detection of a pause frame, MAC data frame transmission stops for a
given pause duration.
pause frames. Upon detection of a pause frame, MAC data frame transmission stops for a
given pause duration.
To enable pause frame detection, the FEC must operate in full-duplex mode (TCR[FDEN]
asserted) and flow control enable (RCR[FCE]) must be asserted. The FEC detects a pause
frame when the fields of the incoming frame match the pause frame specifications, as
shown in the table below. In addition, the receive status associated with the frame should
indicate that the frame is valid.
asserted) and flow control enable (RCR[FCE]) must be asserted. The FEC detects a pause
frame when the fields of the incoming frame match the pause frame specifications, as
shown in the table below. In addition, the receive status associated with the frame should
indicate that the frame is valid.
Pause frame detection is performed by the receiver and microcontroller modules. The
microcontroller runs an address recognition subroutine to detect the specified pause frame
destination address, while the receiver detects the type and opcode pause frame fields. On
detection of a pause frame, TCR[GTS] is asserted by the FEC internally. When
transmission has paused, the EIR[GRA] interrupt is asserted and the pause timer begins to
increment. Note that the pause timer makes use of the transmit backoff timer hardware,
which is used for tracking the appropriate collision backoff time in half-duplex mode. The
pause timer increments once every slot time, until OPD[PAUSE_DUR] slot times have
expired. On OPD[PAUSE_DUR] expiration, TCR[GTS] is deasserted allowing MAC data
frame transmission to resume. Note that the receive flow control pause
(TCR[RFC_PAUSE]) status bit is asserted while the transmitter is paused due to reception
of a pause frame.
microcontroller runs an address recognition subroutine to detect the specified pause frame
destination address, while the receiver detects the type and opcode pause frame fields. On
detection of a pause frame, TCR[GTS] is asserted by the FEC internally. When
transmission has paused, the EIR[GRA] interrupt is asserted and the pause timer begins to
increment. Note that the pause timer makes use of the transmit backoff timer hardware,
which is used for tracking the appropriate collision backoff time in half-duplex mode. The
pause timer increments once every slot time, until OPD[PAUSE_DUR] slot times have
expired. On OPD[PAUSE_DUR] expiration, TCR[GTS] is deasserted allowing MAC data
frame transmission to resume. Note that the receive flow control pause
(TCR[RFC_PAUSE]) status bit is asserted while the transmitter is paused due to reception
of a pause frame.
0d:ff:ff:ff:ff:ff
0x39
57
5d:ff:ff:ff:ff:ff
0x3a
58
7d:ff:ff:ff:ff:ff
0x3b
59
fd:ff:ff:ff:ff:ff
0x3c
60
dd:ff:ff:ff:ff:ff
0x3d
61
9d:ff:ff:ff:ff:ff
0x3e
62
bd:ff:ff:ff:ff:ff
0x3f
63
Table 17-8. PAUSE Frame Field Specification
48-bit Destination Address
0x0180_c200_0001 or Physical Address
48-bit Source Address
Any
16-bit Type
0x8808
16-bit Opcode
0x0001
16-bit PAUSE Duration
0x0000 to 0xFFFF
Table 17-7. Destination Address to 6-Bit Hash (continued)
48-bit DA
6-bit Hash (in
hex)
Hash Decimal
Value