Motorola MCF5281 사용자 설명서

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20-16
MCF5282 User’s Manual
MOTOROLA
 
Memory Map and Registers  
20.5.18 GPT Port Data Register (GPTPORT)
20.5.19 GPT Port Data Direction Register (GPTDDR)
7
6
5
4
3
0
Field
PORTT
Reset
0000_0000
R/W
R/W
Address
IPSBAR + 0x1A_001D, 0x1B_001D
Figure 20-20. GPT Port Data Register (GPTPORT)
Table 20-21. GPTPORT Field Descriptions
Bit(s)
Name
Description
7–4
Reserved, should be cleared.
3–0
PORTT
GPT port input capture/output compare data. Data written to GPTPORT is buffered 
and drives the pins only when they are configured as general-purpose outputs.
Reading an input (DDR bit = 0) reads the pin state; reading an output (DDR bit = 1) 
reads the latched value. Writing to a pin configured as a GPT output does not change 
the pin state. These bits are read anytime (read pin state when corresponding 
PORTTn bit is 0, read pin driver state when corresponding GPTDDR bit is 1), write 
anytime.
7
6
5
4
3
0
Field
DDRT
GPT Function
IC/OC
Pulse Accumulator Function
PAI
Reset
0000_0000
R/W
R/W
Address
IPSBAR + 0x1A_001E, 0x1B_001E
Figure 20-21. GPT Port Data Direction Register (GPTDDR)
Table 20-22. GPTDDR Field Descriptions
Bit(s)
Name
Description
7–4
Reserved, should be cleared.
3–0
DDRT
Control the port logic of PORTTn. Reset clears the PORTTn data direction register, 
configuring all GPT port pins as inputs. These bits are read anytime, write anytime. 
1 Corresponding pin configured as output
0 Corresponding pin configured as input