Motorola MCF5281 사용자 설명서

MOTOROLA

Chapter 21.  DMA Timers (DTIM0–DTIM3)  

21-3

DTMRn[CLK] selects the clock input source. A programmable prescaler divides the clock
input by values from 1 to 256. The prescaler output is an input to the 32-bit counter,
DTCNn.

Each DMA timer has a 32-bit timer capture register (DTCRn) that latches the counter value
when the corresponding input capture edge detector senses a defined DTINn transition. The
capture edge bits (DTMRn[CE]) select the type of transition that triggers the capture and
sets the timer event register capture event bit, DTERn[CAP]. If DTERn[CAP] is set and
DTXMRn[DMAEN] is one, a DMA request is asserted. If DTERn[CAP] is set and
DTXMRn[DMAEN] is zero, an interrupt is asserted.

Each DMA timer can be configured to count up to a reference value, at which point
DTERn[REF] is set. If DTMRn[ORRI] is one and DTXMRn[DMAEN] is zero, an interrupt
is asserted. If DTMRn[ORRI] is one and DTXMRn[DMAEN] is one, a DMA request is
asserted. If the free run/restart bit DTMRn[FRR] is set, a new count starts. If it is clear, the
timer keeps running.

When a timer reaches the reference value selected by DTRR, it can send an output signal
on DTOUTn. DTOUTn can be an active-low pulse or a toggle of the current output as
selected by the TMRn[OM] bit. 

The timer module registers, shown in Table 21-1, can be modified at any time. 

0x400

DMA Timer0 Mode Register (DTMR0)

DMA Timer0 Extended 

Mode Register (DTXMR0) 

DMA Timer0 Event 

Register (DTER0)

0x404

DMA Timer0 Reference Register (DTRR0)

0x408

DMA Timer0 Capture Register (DTCR0)

0x40C

DMA Timer0 Counter Register (DTCN0)

0x440

DMA Timer1 Mode Register (DTMR1)

DMA Timer1 Extended 

Mode Register (DTXMR1) 

DMA Timer1 Event 

Register (DTER1)

0x444

DMA Timer1 Reference Register (DTRR1)