Motorola MCF5281 사용자 설명서

23-12

MOTOROLA

 

Figure 23-8 shows UTBn. TB contains the character in the transmit buffer.

23.3.8 UART Input Port Change Registers (UIPCRn)

The UIPCRs, shown in Figure 23-9, hold the current state and the change-of-state for CTS. 

Table 23-7 describes UIPCRn fields.

7

0

Field

TB

Reset

0000_0000

R/W

Write only

Address

IPSBAR + 0x20C(UTB0), 0x24C(UTB1), 0x28C(UTB2)

Figure 23-8. UART Transmit Buffer (UTBn)

7

5

4

3

1

0

Field

—

COS

—

CTS

Reset

0000

111

CTS

R/W

Read only

Address

IPSBAR + 0x210 (UIPCR0), 0x250 (UIPCR1), 0x290 (UIPCR2)

Figure 23-9. UART Input Port Change Register (UIPCRn)

Table 23-7. UIPCRn Field Descriptions

7–5

—

Reserved, should be cleared.

4

COS

Change of state (high-to-low or low-to-high transition). 
0  No change-of-state since the CPU last read UIPCRn. Reading UIPCRn clears UISRn[COS].
1 A change-of-state longer than 25–50 

µs occurred on the CTS input. UACRn can be programmed to 

generate an interrupt to the CPU when a change of state is detected.

3–1

—

Reserved, should be cleared.

0

CTS

Current state of clear-to-send. Starting two serial clock periods after reset, CTS reflects the state of CTS. If 
CTS is detected asserted at that time, COS is set, which initiates an interrupt if UACRn[IEC] is enabled. 
0  The current state of the CTS input is asserted. 
1  The current state of the CTS input is negated.